In the copending parent application, it is pointed out that there is a need for improved and rapid silicon compound etch processes for integrated circuit manufacture and for glass product manufacture. One of the most important measures of a good etch process is its ability to make clean, walled, high aspect ratio holes. Another important parameter for integrated circuit etch processes is high selectivity for the silicon oxide compounds as opposed to masking, or etch stop materials.
As explained in detail in the above mentioned parent case, in modern integrated circuit manufacture, because of the need for multiple metal interconnect layers, and due to the planarization requirements, the distance from the planarized top surface of an integrated circuit to the underlying low resistance interconnection contacting surfaces across a single chip can now vary widely, i.e., from 5000 .ANG. to 20000 .ANG.. The etch process for VIAS or openings to reach underlying metal must therefore be able to make the deeper holes while at the same time not damaging the materials at the bottom of the shallow holes. To accomplish this result, the etch process must be highly selective so that it does not substantially etch the material in the bottom of the VIA holes while at the same time continuing to rapidly etch the silicon compound of the deeper holes. In addition, the process must make clean side walls of such openings and VIA holes without forming or depositing significant amounts of debris i.e. polymers, on the wall or at the bottom of the openings or holes. In the parent case, a novel process was disclosed for making high aspect ratio VIA holes which is highly selective to TiN and which leaves essentially no polymer in the VIAS. The process disclosed in the parent application employs a high flow rate of a low mass atoms at high elevated pressure (10.0 Torr&gt;p&gt;0.8 Torr) to increase inelastic collision in order to effectively cool the plasma generated by the excitation of CHF.sub.3 and nitrogen gasses using 400 KHz RF source.
There is a need to also provide improved etch processes having selectivity with respect to further materials commonly employed in integrated circuits in addition to TiN.